A semiconductor device is capable of realizing diverse operation by a number of electric devices integrated in a single substrate. For this purpose, various high-technical fabrication methods have been used, and each device in semiconductor device fabrication has been developed to be miniaturized as a component in smaller dimensions.
Semiconductor systems of high-integration and high-capacity have been proposed by developing the technology of packaging semiconductor devices. The semiconductor packaging technology has been changed from a wire bonding to a flip-chip bumping capable of realizing a chip scale, to meet the market requirements.
FIG. 1 is a sectional view illustrating an example of a structure of a conventional ball grid array (BGA) package 10. An individual semiconductor chip 14 is bonded to one side of a substrate 12 for a package by a bonding layer 20, and a part of the semiconductor chip is electrically connected to a part of the substrate by a wire 16. A number of solder bumps 18 are formed on the bottom side of the substrate, and a protecting molding 30 to cover the semiconductor chip and the wire is formed on the top side of the substrate.
As described above, in the conventional art, a substrate with a predetermined thickness is needed for the package of the semiconductor chip. When the semiconductor chip operates, signals are transferred through the electrical interconnection from the wire formed on the top side of the substrate to the solder bumps formed on the bottom side of the substrate. However, as a semiconductor device has been developed, the operation speed of the semiconductor device has been remarkably improved. Then, when an interconnection length within a package is long, a signal is delayed or a distortion is serious upon high-speed operation or high-capacity signal process, thereby failing to satisfy the requirements for various application devices.
Moreover, since the substrate of a predetermined thickness is needed for a package, there are limits in reducing the size and thickness of the whole package. Consequently, the substrate becomes an obstacle in developing communication devices or electronic devices to be small or slim.
Moreover, the conventional BGA package technology has a limit in realizing diverse stacked packages or systemized packages and is not effective in mass production.
Therefore, the present invention is directed to provide a new semiconductor package which is very thin in thickness and simple in structure and which is easily stacked.
Another object of the present invention is to provide a semiconductor package which has a short electrical interconnection length, to be favorable for high speed operation.
Another object of the present invention is to provide a method of fabricating a semiconductor package, which is favorable in mass production and has a simple process.
In accordance with an aspect of the present invention, the present invention provides an ultra slim semiconductor package comprising: a multilayer thin film layer including at least one dielectric layer and at least one or more conductive redistribution layers; at least one semiconductor chip electrically connected to the redistribution layer and mounted on the multilayer thin film layer; conductive structures electrically connected to the redistribution layer and each formed in a post shape at one side of the multilayer thin film layer; a molding part formed on the multilayer thin film layer and at least partially covering the conductive structures and the semiconductor chip; and bumps for external connection or an electrode terminal for external connection formed on the molding part and electrically connected to the conductive structures.
The semiconductor chip may be electrically connected to the multilayer thin film layer by additional separate solder bumps, and in this case, the solder bumps are electrically connected to the conductive structures of the multilayer thin film layer by the redistribution layer.
Alternatively, one side of the semiconductor chip may be directly mounted on the top side of the multilayer thin film layer by die attachment. In this case, an electrode pad is formed at the other side of the semiconductor chip, and the electrode pad is electrically connected to the conductive structures of the multilayer thin film layer by the redistribution layer.
In the semiconductor package according to the present invention, the semiconductor chip is mounted in a face up type. The bottom side of the semiconductor chip may be exposed to the outside or added with a thermal conductive layer, so that heat can be easily spread out.
Further, the interconnection length from the electrode pad of the semiconductor chip to the solder bumps for the external connection is short, so that an electrical signal transfer characteristic is very excellent.
Further, even though the solder ball which is relatively small in size is used as the external connection terminal, since it is electrically connected to the conductive structures in the post shape, stand-off height is high and mechanical reliability is excellent.
In accordance with another aspect of the present invention, the present invention provides a method of fabricating a semiconductor package, comprising steps of: forming a dielectric layer on the top side of a wafer or carrier; forming a conductive redistribution layer on the top side of the dielectric layer; forming conductive structures, each in a post shape, on the redistribution layer, mounting a semiconductor chip on the dielectric layer; forming a molding part on the redistribution layer, to at least partially cover the conductive structures and the semiconductor chip; grinding the top side of the molding part; and forming bumps for external connection so as to be electrically connected to the conductive structures.
In accordance with the fabrication method, since the package structure is maintained only by mold, without any additional substrate for the package, the package thickness is formed to be very thin and the size thereof is easily controlled. Furthermore, since the conductive redistribution layer and the conductive structures in the post shape are formed at wafer level or carrier level, the process is easy and the fabrication cost is reduced. Specifically, it is easy to stack a plurality of the packages at wafer level.